Internia

Intel Interview Experiences

Software Developer

San Jose, CA

Summer 2025No Offer

Arizona State University · Computer Science

1st year · 2.9-3.2 GPA · 0 past internships

Easy Interview

TechnicalMultiple roundsVirtualResume Review

One way video then live interview with HR and managers. All STAR about learning something new and supply chain scenarios. Intel company values questions and I only knew the obvious ones

Questions Asked

  1. 1.What is continuous integration and what problem does it solve?

Computer Engineering

San Jose, CA

Summer 2026Accepted

Georgia Tech · Computer Engineering

4th year · 3.7+ GPA · 2 past internships

Hard Interview

TechnicalMultiple roundsVirtualConversational

Passed recruiter screen, first technical was graph BFS and solved it no issues but second technical had a really long problem statement like two pages and by the time I understood what they wanted I only had 20 minutes to code and didn't finish

Questions Asked

  1. 1.Tell me about an embedded or hardware project you designed and built

Software Engineer

San Jose, CA

Winter 2025Accepted

University of Illinois Urbana-Champaign · Computer Science

4th year · 3.3-3.6 GPA · 3 past internships

Hard Interview

TechnicalMultiple roundsVirtual

Ninety minutes felt like a panel. Three 30 min segmennts back to back, DSA and OOP first, then systems questions on CPU scheduling and memory hierarchy, then fit. Intel specific knowledge helps even for SWE

Questions Asked

  1. 1.How would you profile a slow database query?

Module Engineer

Summer 2026Pending Outcome

University of Waterloo · Software Engineer

3rd Year · 3.7+ GPA · 0 past internships

Technical

1 interview. The interview is mostly chill. No technical question are asked.

Hardware Engineer

San Jose, CA

Winter 2026No Offer

Purdue University · Electrical Engineering

4th year · 3.3-3.6 GPA · 2 past internships

Hard Interview

TechnicalVirtual

Domain stuff matters more than coding here. Phone screen, then technical on semiconductor processes and VLSI design. Got a question about propagation delay and power tradeoffs I only partially answered. Coding at the end was easier

Questions Asked

  1. 1.What causes priority inversion and how do you solve it?
  2. 2.What is JTAG used for in hardware development?

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